D8.1 AArch64 AMU register summary

The following table gives a summary of the Cortex®‑A76 AMU registers in the AArch64 Execution state.

Table D8-1 AArch64 AMU registers

Name Width Reset Description
AMCNTENCLR_EL0 32 0x00000000 D8.2 AMCNTENCLR0_EL0, Activity Monitors Count Enable Clear Register, EL0
AMCNTENSET_EL0 32 0x00000000 D8.3 AMCNTENSET_EL0, Activity Monitors Count Enable Set Register, EL0
AMCFGR_EL0 32 0x00003F04 D8.4 AMCFGR_EL0, Activity Monitors Configuration Register, EL0
AMUSERENR_EL0 32 0x00000000 D8.5 AMUSERENR_EL0, Activity Monitor EL0 Enable access, EL0
AMEVCNTRn_EL0 64 0x0000000000000000 D8.6 AMEVCNTRn_EL0, Activity Monitor Event Counter Register, EL0
AMEVTYPERn_EL0 32

The reset value depends on the register:

  • AMEVTYPER0_EL0 = 0x00000011.
  • AMEVTYPER1_EL0 = 0x000000EF.
  • AMEVTYPER2_EL0 = 0x00000008.
  • AMEVTYPER3_EL0 = 0x000000F0.
  • AMEVTYPER4_EL0 = 0x000000F1.
D8.7 AMEVTYPERn_EL0, Activity Monitor Event Type Register, EL0
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