B.1 Revisions

This appendix describes the technical changes between released issues of this book

Table B-1 Issue 0000-00

Change Location Affects

First release

- -

Table B-2 Differences between Issue 0000-00 and Issue 0100-00

Change Location Affects

Added support for 128KB L2 cache size.

Throughout document r1p0

Added note to indicate support for Dot Product instructions introduced in the Armv8.4 Extension.

A1.1 About the core r1p0

Updated BPIQ data location encoding table.

A6.6.1 Encoding for L1 instruction cache tag, L1 instruction cache data, L1 BTB, L1 GHB, L1 TLB instruction, and BPIQ r1p0

Updated replacement policy to dynamic biased replacement policy.

A7.1 About the L2 memory system r1p0

Updated reset values for ID_AA64ISAR0_EL1, IDAA64MMFR1_EL1, IDMMFR4_EL1, and MIDR_EL1.

B2.4 AArch64 registers by functional group r1p0

Updated CCSIDR_EL1 encodings table.

B2.18 CCSIDR_EL1, Cache Size ID Register, EL1 r1p0

Updated CPUECTLR_EL1 register description.

B2.27 CPUECTLR_EL1, CPU Extended Control Register, EL1 r1p0

Updated bits [43:32] of ID_AA64ISAR0_EL1 register.

B2.57 ID_AA64ISAR0_EL1, AArch64 Instruction Set Attribute Register 0, EL1 r1p0

Updated bits [15:12] of ID_AA64MMFR1_EL1 register.

B2.60 ID_AA64MMFR1_EL1, AArch64 Memory Model Feature Register 1, EL1 r1p0

Added ID_ISAR6_EL1 register.

B2.72 ID_ISAR6_EL1, AArch32 Instruction Set Attribute Register 6, EL1 r1p0

Added Activity Monitor Unit chapter.

Chapter C3 Activity Monitor Unit All versions

Updated reset value for TRCIDR1 register.

D9.1 ETM register summary r1p0

Updated bits [3:0] of TRCIDR1 register.

D9.30 TRCIDR1, ID Register 1 r1p0

Table B-3 Differences between Issue 0100-00 and Issue 0200-00

Change Location Affects

Fixed typographical errors.

Throughout document -

Added information for L1 Prefetch History Table.

Table   A8-1 Cache protection behavior r2p0

Updated ATCR_EL12 description.

Table   B2-3 AArch64 implementation defined registers r2p0

Updated reset value for ID_AA64PFR0_EL1.

B2.4 AArch64 registers by functional group r2p0

Updated reset value for ID_PFR0_EL1.

B2.4 AArch64 registers by functional group r2p0

Added new register ID_PFR2_EL1.

B2.4 AArch64 registers by functional group

B2.80 ID_PFR2_EL1, AArch32 Processor Feature Register 2, EL1

r2p0

Updated reset value for MIDR_EL1.

B2.4 AArch64 registers by functional group

B2.85 MIDR_EL1, Main ID Register, EL1

r2p0

Added CSV2 and CSV3 fields to register.

B2.62 ID_AA64PFR0_EL1, AArch64 Processor Feature Register 0, EL1 r2p0

Added CSV2 field to register.

B2.78 ID_PFR0_EL1, AArch32 Processor Feature Register 0, EL1 r2p0

Added TRCVMIDCCTLR0 register description.

D9.76 TRCVMIDCCTLR0, Virtual context identifier Comparator Control Register 0 r2p0

Table B-4 Differences between Issue 0200-00 and Issue 0300-00

Change Location Affects

Fixed typographical errors.

Throughout document -

Added new register ID_AA64PFR1_EL1.

B2.63 ID_AA64PFR1_EL1, AArch64 Processor Feature Register 1, EL1 r3p0

Updated reset value for ID_PFR2_EL1.

B2.4 AArch64 registers by functional group r3p0

Updated reset value for MIDR_EL1.

B2.4 AArch64 registers by functional group r3p0

Updated reset value for TRCIDR1.

D9.1 ETM register summary r3p0

Added SSBS field to ID_AA64PFR1_EL1.

B2.63 ID_AA64PFR1_EL1, AArch64 Processor Feature Register 1, EL1

r3p0

Table B-5 Differences between Issue 0300-00 and Issue 0301-00

Change Location Affects

Updated reset value for MIDR_EL1.

B2.4 AArch64 registers by functional group r3p1
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