D5.2 PMCEID0_EL0, Performance Monitors Common Event Identification Register 0, EL0

The PMCEID0_EL0 defines which common architectural and common microarchitectural feature events are implemented.

Bit field descriptions

Figure D5-1 PMCEID0_EL0 bit assignments
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ID[31:0], [31:0]

Common architectural and microarchitectural feature events that can be counted by the PMU event counters.

For each bit described in the following table, the event is implemented if the bit is set to 1, or not implemented if the bit is set to 0.

Table D5-2 PMU common events

Bit Event mnemonic Description
[31] L1D_CACHE_ALLOCATE

L1 Data cache allocate:

0This event is not implemented.
[30] CHAIN

Chain. For odd-numbered counters, counts once for each overflow of the preceding even-numbered counter. For even-numbered counters, does not count:

1This event is implemented.
[29] BUS_CYCLES

Bus cycle:

1This event is implemented.
[28] TTBR_WRITE_RETIRED

TTBR write, architecturally executed, condition check pass - write to translation table base:

1This event is implemented.
[27] INST_SPEC

Instruction speculatively executed:

1This event is implemented.
[26] MEMORY_ERROR

Local memory error:

1This event is implemented.
[25] BUS_ACCESS

Bus access:

1This event is implemented.
[24] L2D_CACHE_WB

L2 Data cache Write-Back:

1This event is implemented.
[23] L2D_CACHE_REFILL

L2 Data cache refill:

1This event is implemented.
[22] L2D_CACHE

L2 Data cache access:

1This event is implemented.
[21] L1D_CACHE_WB

L1 Data cache Write-Back:

1This event is implemented.
[20] L1I_CACHE

L1 Instruction cache access:

1This event is implemented.
[19] MEM_ACCESS

Data memory access:

1This event is implemented.
[18] BR_PRED

Predictable branch speculatively executed:

1This event is implemented.
[17] CPU_CYCLES

Cycle:

1This event is implemented.
[16] BR_MIS_PRED

Mispredicted or not predicted branch speculatively executed:

1This event is implemented.
[15] UNALIGNED_LDST_RETIRED

Instruction architecturally executed, condition check pass - unaligned load or store:

0This event is not implemented.
[14] BR_RETURN_RETIRED

Instruction architecturally executed, condition check pass - procedure return:

0This event is not implemented.
[13] BR_IMMED_RETIRED

Instruction architecturally executed - immediate branch:

0This event is not implemented.
[12] PC_WRITE_RETIRED

Instruction architecturally executed, condition check pass - software change of the PC:

0This event is not implemented.
[11] CID_WRITE_RETIRED

Instruction architecturally executed, condition check pass - write to CONTEXTIDR:

1This event is implemented.
[10] EXC_RETURN

Instruction architecturally executed, condition check pass - exception return:

1This event is implemented.
[9] EXC_TAKEN

Exception taken:

1This event is implemented.
[8] INST_RETIRED

Instruction architecturally executed:

1This event is implemented.
[7] ST_RETIRED

Instruction architecturally executed, condition check pass - store:

0This event is not implemented.
[6] LD_RETIRED

Instruction architecturally executed, condition check pass - load:

0This event is not implemented.
[5] L1D_TLB_REFILL

L1 Data TLB refill:

1This event is implemented.
[4] L1D_CACHE

L1 Data cache access:

1This event is implemented.
[3] L1D_CACHE_REFILL

L1 Data cache refill:

1This event is implemented.
[2] L1I_TLB_REFILL

L1 Instruction TLB refill:

1This event is implemented.
[1] L1I_CACHE_REFILL

L1 Instruction cache refill:

1This event is implemented.
[0] SW_INCR

Instruction architecturally executed, condition check pass - software increment:

1This event is implemented.

Note:

The PMU events implemented in the above table can be found in Table   C2-1 .
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