A5.5.2 Descriptor hardware update

The core supports hardware update in AArch64 state using hardware management of the access flag and hardware management of dirty state.

These features are enabled in registers TCR_ELx and VTCR_EL2.

Hardware management of the Access flag is enabled by the following configuration fields:

  • TCR_ELx.HA for stage 1 translations.
  • VTCR_EL2.HA for stage 2 translations.

Hardware management of dirty state is enabled by the following configuration fields:

  • TCR_ELx.HD for stage 1 translations.
  • VTCR_EL2.HD for stage 2 translations.

Note:

Hardware management of dirty state can only be enabled if hardware management of the Access flag is enabled.

To support the hardware management of dirty state, the DBM field is added to the translation table descriptors as part of Armv8.1 architecture.

The core supports hardware update only in outer Write-Back and inner Write-Back memory regions.

If software requests a hardware update in a memory region that is not inner Write-Back or not outer Write-Back, then the core returns an abort with the following encoding:

  • ESR.ELx.DFSC = 0b110001 for Data Aborts in AArch64.
  • ESR.ELx.IFSC = 0b110001 for Instruction Aborts in AArch64.
Non-ConfidentialPDF file icon PDF version100798_0301_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.