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The Cortex®‑A76 core provides a mechanism to read the internal memory that is used by the L1 caches, L2 cache, and TLB structures through implementation defined system registers. This functionality can be useful when debugging software or hardware issues.
When the core executes in AArch64 state, there are six read-only registers that are used to access the contents of the internal memory. The internal memory is selected by programming the implementation-defined RAMINDEX register (using SYS #6, c15, c0, #0 instruction). These operations are available only in EL3. In all other modes, executing these instructions results in an Undefined Instruction exception. The data is read from read-only registers as shown in the following table.
Table A6-1 AArch64 registers used to access internal memory
|Register name||Function||Access||Operation||Rd Data|
|IDATA0_EL3||Instruction Register 0||Read-only||
|IDATA1_EL3||Instruction Register 1||Read-only||
|IDATA2_EL3||Instruction Register 2||Read-only||
|DDATA0_EL3||Data Register 0||Read-only||
|DDATA1_EL3||Data Register 1||Read-only||
|DDATA2_EL3||Data Register 2||Read-only||