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Arm® Cortex®‑A76 Core Technical Reference ManualRevision r3p1
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B4.13 ICV_AP0R0_EL1, Interrupt Controller Virtual Active Priorities Group 0 Register 0, EL1

The ICV_AP0R0_EL1 register provides information about virtual Group 0 active priorities.

Bit descriptions

This register is a 32-bit register and is part of the virtual GIC system registers functional group.

The core implements 5 bits of priority with 32 priority levels, corresponding to the 32 bits [31:0] of the register. The possible values for each bit are:

0x00000000No interrupt active. This is the reset value.
0x00000001Interrupt active for priority 0x0.
0x00000002Interrupt active for priority 0x8.
...
0x80000000Interrupt active for priority 0xF8.

Details that are not provided in this description are architecturally defined. See the Arm® Generic Interrupt Controller Architecture Specification.

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