C1.3.1 Watchpoint debug events

In the Cortex®‑A76 core, watchpoint debug events are always synchronous.

Memory hint instructions and cache clean operations, except DC ZVA and DC IVAC, do not generate watchpoint debug events. Store exclusive instructions generate a watchpoint debug event even when the check for the control of exclusive monitor fails. Atomic CAS instructions generate a watchpoint debug event even when the compare operation fails.

Non-ConfidentialPDF file icon PDF version100798_0301_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.