D5.1 AArch64 PMU register summary

The PMU counters and their associated control registers are accessible in the AArch64 Execution state with MRS and MSR instructions.

The following table gives a summary of the Cortex®‑A76 PMU registers in the AArch64 Execution state. For those registers not described in this chapter, see the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

Table D5-1 PMU register summary in the AArch64 Execution state

Name Type Width Reset Description
PMCR_EL0 RW 32 0x410B30XX D5.4 PMCR_EL0, Performance Monitors Control Register, EL0
PMCNTENSET_EL0 RW 32 UNK

Performance Monitors Count Enable Set Register

PMCNTENCLR_EL0 RW 32 UNK

Performance Monitors Count Enable Clear Register

PMOVSCLR_EL0 RW 32 UNK

Performance Monitors Overflow Flag Status Register

PMSWINC_EL0 WO 32 UNK

Performance Monitors Software Increment Register

PMSELR_EL0 RW 32 UNK

Performance Monitors Event Counter Selection Register

PMCEID0_EL0 RO 64

0xF7FF0F3F

D5.2 PMCEID0_EL0, Performance Monitors Common Event Identification Register 0, EL0
PMCEID1_EL0 RO 64

0x0000BE7F

D5.3 PMCEID1_EL0, Performance Monitors Common Event Identification Register 1, EL0
PMCCNTR_EL0 RW 64 UNK

Performance Monitors Cycle Count Register

PMXEVTYPER_EL0 RW 32 UNK Performance Monitors Selected Event Type and Filter Register
PMCCFILTR_EL0 RW 32 UNK

Performance Monitors Cycle Count Filter Register

PMXEVCNTR_EL0 RW 32 UNK Performance Monitors Selected Event Count Register
PMUSERENR_EL0 RW 32 UNK

Performance Monitors User Enable Register

PMINTENSET_EL1 RW 32 UNK

Performance Monitors Interrupt Enable Set Register

PMINTENCLR_EL1 RW 32 UNK

Performance Monitors Interrupt Enable Clear Register

PMOVSSET_EL0 RW 32 UNK Performance Monitors Overflow Flag Status Set Register
PMEVCNTR0_EL0 RW 32 UNK Performance Monitors Event Count Registers
PMEVCNTR1_EL0 RW 32 UNK
PMEVCNTR2_EL0 RW 32 UNK
PMEVCNTR3_EL0 RW 32 UNK
PMEVCNTR4_EL0 RW 32 UNK
PMEVCNTR5_EL0 RW 32 UNK
PMEVTYPER0_EL0 RW 32 UNK

Performance Monitors Event Type Registers

PMEVTYPER1_EL0 RW 32 UNK
PMEVTYPER2_EL0 RW 32 UNK
PMEVTYPER3_EL0 RW 32 UNK
PMEVTYPER4_EL0 RW 32 UNK
PMEVTYPER5_EL0 RW 32 UNK
PMCCFILTR_EL0 RW 32 UNK

Performance Monitors Cycle Count Filter Register

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