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This section describes the interaction with the PMU and the effect of debug double lock on trace register access.
The Cortex®‑A76 core includes a PMU that enables events, such as cache misses and instructions executed, to be counted over a period of time.
The PMU and ETM trace unit function together.
The PMU architectural events described in C2.3 PMU events are available to the ETM trace unit through the extended input facility.
See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for more information about PMU events.
The ETM trace unit uses four extended external input selectors to access the PMU events. Each selector can independently select one of the PMU events, that are then active for the cycles where the relevant events occur. These selected events can then be accessed by any of the event registers within the ETM trace unit. The PMU event table describes the PMU events.