B2.77 ID_MMFR4_EL1, AArch32 Memory
Model Feature Register 4, EL1
The ID_MMFR4_EL1 provides information about the memory model and memory management support in AArch32.
Bit field descriptions
ID_MMFR4_EL1 is a 32-bit register, and is part of the Identification
registers functional group.
This register is Read Only.
B2-61 ID_MMFR4_EL1 bit assignments
- RAZ, [31:24]
- LSM, [23:20]
- Load/Store Multiple. Indicates whether adjacent loads or stores can be
combined. The value is:
|LSMAOE and nTLSMD bit not supported.
- HD, [19:16]
Presence of Hierarchical Disables. Enables an operating system or hypervisor to hand over up to 4 bits of the last level page table descriptor (bits[62:59] of the page table entry) for use by hardware for IMPLEMENTATION DEFINED usage. The value is:
Hierarchical Permission Disables and Hardware allocation of bits[62:59] supported.
- CNP, [15:12]
- Common Not Private. Indicates support for selective sharing of TLB
entries across multiple PEs. The value is:
- XNX, [11:8]
- Execute Never. Indicates whether the stage 2 translation tables allows
the stage 2 control of whether memory is executable at EL1 independent of whether memory
is executable at EL0. The value is:
|EL0/EL1 execute control distinction at stage2 bit
- AC2, [7:4]
- Indicates the extension of the ACTLR and HACTLR registers using ACTLR2
and HACTLR2. The value is:
|ACTLR2 and HACTLR2 are implemented.
- SpecSEI, [3:0]
- Describes whether the core can generate SError interrupt
exceptions from speculative reads of memory, including speculative instruction fetches.
The value is:
|The core never generates an SError interrupt due to an
external abort on a speculative read.
There is one copy of this register that is used in both Secure and
Must be interpreted with ID_MMFR0_EL1, ID_MMFR1_EL1, ID_MMFR2_EL1, and
Bit fields and details that are not provided in this description are
architecturally defined. See the
Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.