|Home > Register descriptions > AArch64 system registers > ID_AA64MMFR1_EL1, AArch64 Memory Model Feature Register 1, EL1|
The ID_AA64MMFR1_EL1 provides information about the implemented memory model and memory management support in the AArch64 Execution state.
ID_AA64MMFR1_EL1 is a 64-bit register, and is part of the Identification registers functional group.
This register is Read Only.
Indicates whether provision of EL0 vs EL1 execute never control at Stage 2 is supported.
|EL0/EL1 execute control distinction at Stage 2 bit is supported. All other values are reserved.|
Describes whether the PE can generate SError interrupt exceptions from speculative reads of memory, including speculative instruction fetches.
|The PE never generates an SError interrupt due to an external abort on a speculative read.|
Privileged Access Never. Indicates support for the PAN bit in PSTATE, SPSR_EL1, SPSR_EL2, SPSR_EL3, and DSPSR_EL0.
|PAN supported and AT S1E1RP and AT S1E1WP instructions supported.|
Indicates support for LORegions.
Presence of Hierarchical Disables. Enables an operating system or hypervisor to hand over up to 4 bits of the last level page table descriptor (bits[62:59] of the page table entry) for use by hardware for IMPLEMENTATION DEFINED usage. The value is:
Hierarchical Permission Disables and Hardware allocation of bits[62:59] supported.
Indicates whether Virtualization Host Extensions are supported.
|Virtualization Host Extensions supported.|
Indicates the number of VMID bits supported.
|16 bits are supported.|
Indicates the support for hardware updates to Access flag and dirty state in translation tables.
|Hardware update of both the Access flag and dirty state is supported in hardware.|
There are no configuration notes.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.