B2.37 ERRIDR_EL1, Error ID Register, EL1

The ERRIDR_EL1 defines the number of error record registers.

Bit field descriptions

ERRIDR_EL1 is a 32-bit register, and is part of the registers Reliability, Availability, Serviceability (RAS) functional group.

This register is Read Only.

Figure B2-33 ERRIDR_EL1 bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


RES0, [31:16]
res0 Reserved.
NUM, [15:0]

Number of records that can be accessed through the Error Record system registers.

0x0002

Two records present.

Configurations

There are no configuration notes.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

Non-ConfidentialPDF file icon PDF version100798_0301_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.