B5.2 FPCR, Floating-point Control Register

The FPCR controls floating-point behavior.

Bit field descriptions

FPCR is a 32-bit register.

Figure B5-1 FPCR bit assignments
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RES0, [31:27]
res0Reserved.
AHP, [26]

Alternative half-precision control bit. The possible values are:

0IEEE half-precision format selected. This is the reset value.
1Alternative half-precision format selected.
DN, [25]

Default NaN mode control bit. The possible values are:

0NaN operands propagate through to the output of a floating-point operation. This is the reset value.
1Any operation involving one or more NaNs returns the Default NaN.
FZ, [24]

Flush-to-zero mode control bit. The possible values are:

0Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant with the IEEE 754 standard. This is the reset value.
1Flush-to-zero mode enabled.
RMode, [23:22]

Rounding Mode control field. The encoding of this field is:

0b00Round to Nearest (RN) mode. This is the reset value.
0b01Round towards Plus Infinity (RP) mode.
0b10Round towards Minus Infinity (RM) mode.
0b11Round towards Zero (RZ) mode.
RES0, [21:20]
res0Reserved.
FZ16, [19]

Flush-to-zero mode control bit on half-precision data-processing instructions. The possible values are:

0Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant with the IEEE 754 standard. This is the default value.
1Flush-to-zero mode enabled.
RES0, [18:0]
res0Reserved.
Configurations
The named fields in this register map to the equivalent fields in the AArch32 FPSCR. See B5.8 FPSCR, Floating-Point Status and Control Register.

Usage constraints

Accessing the FPCR

To access the FPCR:

MRS <Xt>, FPCR ; Read FPCR into Xt
MSR FPCR, <Xt> ; Write Xt to FPCR

Register access is encoded as follows:

Table B5-2 FPCR access encoding

op0 op1 CRn CRm op2
11 011 0100 0100 000
Accessibility
This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

RW RW RW RW RW RW
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