B2.7 ACTLR_EL3, Auxiliary Control Register, EL3

The ACTLR_EL3 provides IMPLEMENTATION DEFINED configuration and control options for EL3.

Bit field descriptions

ACTLR_EL3 is a 64-bit register, and is part of:

  • The Other system control registers functional group.
  • The Security registers functional group.
  • The IMPLEMENTATION DEFINED functional group.
Figure B2-3 ACTLR_EL3 bit assignments
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RES0, [63:13]
RES0 Reserved.
CLUSTERPMUEN, [12]

Performance Management Registers enable. The possible values are:

0CLUSTERPM* registers are not write-accessible from a lower Exception level. This is the reset value.
1CLUSTERPM* registers are write-accessible from EL2 and EL1 Secure.
SMEN, [11]

Scheme Management Registers enable. The possible values are:

0Registers CLUSTERACPSID, CLUSTERSTASHSID, CLUSTERPARTCR, CLUSTERBUSQOS, and CLUSTERTHREADSIDOVR are not write-accessible from EL2 and EL1 Secure. This is the reset value.
1Registers CLUSTERACPSID, CLUSTERSTASHSID, CLUSTERPARTCR, CLUSTERBUSQOS, and CLUSTERTHREADSIDOVR are write-accessible from EL2 and EL1 Secure.
TSIDEN, [10]

Thread Scheme ID Register enable. The possible values are:

0Register CLUSTERTHREADSID is not write-accessible from EL2 and EL1 Secure. This is the reset value.
1Register CLUSTERTHREADSID is write-accessible from EL2 and EL1 Secure.
RES0, [9:8]
RES0Reserved.
PWREN, [7]

Power Control Registers enable. The possible values are:

0Registers CPUPWRCTLR, CLUSTERPWRCTLR, CLUSTERPWRDN, CLUSTERPWRSTAT, CLUSTERL3HIT and CLUSTERL3MISS are not write-accessible from EL2 and EL1 Secure. This is the reset value.
1Registers CPUPWRCTLR, CLUSTERPWRCTLR, CLUSTERPWRDN, CLUSTERPWRSTAT, CLUSTERL3HIT and CLUSTERL3MISS are write-accessible from EL2 and EL1 Secure.
RES0, [6]
RES0Reserved.
ERXPFGEN, [5]

Error Record Registers enable. The possible values are:

0ERXPFG* are not write-accessible from EL2 and EL1 Secure. This is the reset value.
1ERXPFG* are write-accessible from EL2 and EL1 Secure.
AMEN, [4]

Activity Monitor enable. The possible values are:

0Accesses from EL2, EL1 and EL0 to activity monitor registers are trapped to EL3.
1Accesses from EL2, EL1 and EL0 to activity monitor registers are not trapped to EL3.
RES0, [3:2]
RES0Reserved.
ECTLREN, [1]

Extended Control Registers enable. The possible values are:

0CPUECTLR and CLUSTERECTLR are not write-accessible from EL2 and EL1 Secure. This is the reset value.
1CPUECTLR and CLUSTERECTLR are write-accessible from EL2 and EL1 Secure.
Configurations

Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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