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The HCR_EL2 provides configuration control for virtualization, including whether various Non-secure operations are trapped to EL2.
HCR_EL2 is a 64-bit register, and is part of the Virtualization registers functional group.
Mismatched Inner/Outer Cacheable Non-Coherency Enable, for the Non-secure EL1 and EL0 translation regime.
Traps general exceptions. If this bit is set, and SCR_EL3.NS is set, then:
0regardless of its actual state, other than for reading the bit.
1regardless of their actual state, other than for reading the bits.
HCR_EL2.TGE must not be cached in a TLB.
When the value of SCR_EL3.NS is 0 the core behaves as if this field is 0 for all purposes other than a direct read or write access of HCR_EL2.
Traps ID group 3 registers. The possible values are:
| ||ID group 3 register accesses are not trapped.|
| ||Reads to ID group 3 registers executed from Non-secure EL1 are trapped to EL2.|
See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for the registers covered by this setting.
If EL2 is not implemented, this register is RES0 from EL3
RW fields in this register reset to architecturally UNKNOWN values.
Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.