Bit field descriptions

ID_AA64MMFR0_EL1 is a 64-bit register, and is part of the Identification registers functional group.

This register is Read Only.

RES0, [63:32]

RES0

Reserved.

TGran4, [31:28]

Support for 4KB memory translation granule size:

0x0	4KB granule supported.

TGran64, [27:24]

Support for 64KB memory translation granule size:

0x0	64KB granule supported.

TGran16, [23:20]

Support for 16KB memory translation granule size:

0x1	Indicates that the 16KB granule is supported.

BigEndEL0, [19:16]

Mixed-endian support only at EL0.

0x0	No mixed-endian support at EL0. The SCTLR_EL1.E0E bit has a fixed value.

SNSMem, [15:12]

Secure versus Non-secure Memory distinction:

0x1	Supports a distinction between Secure and Non-secure Memory.

BigEnd, [11:8]

Mixed-endian configuration support:

0x1	Mixed-endian support. The SCTLR_ELx.EE and SCTLR_EL1.E0E bits can be configured.

ASIDBits, [7:4]

Number of ASID bits:

0x2

16 bits.

PARange, [3:0]

Physical address range supported:

0x2	40 bits, 1TB. The supported Physical Address Range is 40-bits. Other cores in the DSU may support a different Physical Address Range.

Configurations

There are no configuration notes.

Bit fields and details that are not provided in this description are architecturally defined. See the Arm^® Architecture Reference Manual Armv8, for Armv8-A architecture profile.