B2.59 ID_AA64MMFR0_EL1, AArch64 Memory Model Feature Register 0, EL1

The ID_AA64MMFR0_EL1 provides information about the implemented memory model and memory management support in the AArch64 Execution state.

Bit field descriptions

ID_AA64MMFR0_EL1 is a 64-bit register, and is part of the Identification registers functional group.

This register is Read Only.

Figure B2-43 ID_AA64MMFR0_EL1 bit assignments
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RES0, [63:32]
TGran4, [31:28]

Support for 4KB memory translation granule size:

0x04KB granule supported.
TGran64, [27:24]

Support for 64KB memory translation granule size:

0x064KB granule supported.
TGran16, [23:20]

Support for 16KB memory translation granule size:

0x1Indicates that the 16KB granule is supported.
BigEndEL0, [19:16]

Mixed-endian support only at EL0.

0x0No mixed-endian support at EL0. The SCTLR_EL1.E0E bit has a fixed value.
SNSMem, [15:12]

Secure versus Non-secure Memory distinction:

0x1Supports a distinction between Secure and Non-secure Memory.
BigEnd, [11:8]

Mixed-endian configuration support:

0x1Mixed-endian support. The SCTLR_ELx.EE and SCTLR_EL1.E0E bits can be configured.
ASIDBits, [7:4]

Number of ASID bits:

0x216 bits.
PARange, [3:0]

Physical address range supported:


40 bits, 1TB.

The supported Physical Address Range is 40-bits. Other cores in the DSU may support a different Physical Address Range.


There are no configuration notes.

Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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