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Home > Register descriptions > AArch64 system registers > ID_AA64MMFR0_EL1, AArch64 Memory Model Feature Register 0, EL1 |
The ID_AA64MMFR0_EL1 provides information about the implemented memory model and memory management support in the AArch64 Execution state.
ID_AA64MMFR0_EL1 is a 64-bit register, and is part of the Identification registers functional group.
This register is Read Only.
RES0 | Reserved. |
Support for 4KB memory translation granule size:
0x0 | 4KB granule supported. |
Support for 64KB memory translation granule size:
0x0 | 64KB granule supported. |
Support for 16KB memory translation granule size:
| Indicates that the 16KB granule is supported. |
Mixed-endian support only at EL0.
| No mixed-endian support at EL0. The SCTLR_EL1.E0E bit has a fixed value. |
Secure versus Non-secure Memory distinction:
0x1 | Supports a distinction between Secure and Non-secure Memory. |
Mixed-endian configuration support:
0x1 | Mixed-endian support. The SCTLR_ELx.EE and SCTLR_EL1.E0E bits can be configured. |
Number of ASID bits:
0x2 | 16 bits. |
Physical address range supported:
0x2 |
40 bits, 1TB. The supported Physical Address Range is 40-bits. Other cores in the DSU may support a different Physical Address Range. |
There are no configuration notes.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.