B2.69 ID_ISAR3_EL1, AArch32 Instruction Set Attribute Register 3, EL1

The ID_ISAR3_EL1 provides information about the instruction sets implemented by the core in AArch32.

Bit field descriptions

ID_ISAR3_EL1 is a 32-bit register, and is part of the Identification registers functional group.

This register is Read Only.

Figure B2-53 ID_ISAR3_EL1 bit assignments
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T32EE, [31:28]

Indicates the implemented T32EE instructions:

0x0 None implemented.
TrueNOP, [27:24]

Indicates support for True NOP instructions:

0x1 True NOP instructions in both the A32 and T32 instruction sets, and additional NOP-compatible hints.
T32Copy, [23:20]

Indicates the support for T32 non flag-setting MOV instructions:

0x1 Support for T32 instruction set encoding T1 of the MOV (register) instruction, copying from a low register to a low register.
TabBranch, [19:16]

Indicates the implemented Table Branch instructions in the T32 instruction set.

0x1 The TBB and TBH instructions.
SynchPrim, [15:12]

Indicates the implemented Synchronization Primitive instructions:

0x2
  • The LDREX and STREX instructions.
  • The CLREX, LDREXB, STREXB, and STREXH instructions.
  • The LDREXD and STREXD instructions.
SVC, [11:8]

Indicates the implemented SVC instructions:

0x1 The SVC instruction.
SIMD, [7:4]

Indicates the implemented Single Instruction Multiple Data (SIMD) instructions.

0x3
  • The SSAT and USAT instructions, and the Q bit in the PSRs.
  • The PKHBT, PKHTB, QADD16, QADD8, QASX, QSUB16, QSUB8, QSAX, SADD16, SADD8, SASX, SEL, SHADD16, SHADD8, SHASX, SHSUB16, SHSUB8, SHSAX, SSAT16, SSUB16, SSUB8, SSAX, SXTAB16, SXTB16, UADD16, UADD8, UASX, UHADD16, UHADD8, UHASX, UHSUB16, UHSUB8, UHSAX, UQADD16, UQADD8, UQASX, UQSUB16, UQSUB8, UQSAX, USAD8, USADA8, USAT16, USUB16, USUB8, USAX, UXTAB16, UXTB16 instructions, and the GE[3:0] bits in the PSRs.
The SIMD field relates only to implemented instructions that perform SIMD operations on the general-purpose registers. In an implementation that supports Advanced SIMD and floating-point instructions, MVFR0, MVFR1, and MVFR2 give information about the implemented Advanced SIMD instructions.
Saturate, [3:0]

Indicates the implemented Saturate instructions:

0x1 The QADD, QDADD, QDSUB, QSUB Q bit in the PSRs.
Configurations

In an AArch64-only implementation, this register is UNKNOWN.

Must be interpreted with ID_ISAR0_EL1, ID_ISAR1_EL1, ID_ISAR2_EL1, ID_ISAR4_EL1, ID_ISAR5_EL1, and ID_ISAR6_EL1. See:

Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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