B2.74 ID_MMFR1_EL1, AArch32 Memory Model Feature Register 1, EL1

The ID_MMFR1_EL1 provides information about the memory model and memory management support in AArch32.

Bit field descriptions

ID_MMFR1_EL1 is a 32-bit register, and is part of the Identification registers functional group.

This register is Read Only.

Figure B2-58 ID_MMFR1_EL1 bit assignments
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BPred, [31:28]

Indicates branch predictor management requirements:

0x4 For execution correctness, branch predictor requires no flushing at any time.
L1TstCln, [27:24]

Indicates the supported L1 Data cache test and clean operations, for Harvard or unified cache implementation:

0x0 None supported.
L1Uni, [23:20]

Indicates the supported entire L1 cache maintenance operations, for a unified cache implementation:

0x0 None supported.
L1Hvd, [19:16]

Indicates the supported entire L1 cache maintenance operations, for a Harvard cache implementation:

0x0 None supported.
L1UniSW, [15:12]

Indicates the supported L1 cache line maintenance operations by set/way, for a unified cache implementation:

0x0 None supported.
L1HvdSW, [11:8]

Indicates the supported L1 cache line maintenance operations by set/way, for a Harvard cache implementation:

0x0 None supported.
L1UniVA, [7:4]

Indicates the supported L1 cache line maintenance operations by MVA, for a unified cache implementation:

0x0 None supported.
L1HvdVA, [3:0]

Indicates the supported L1 cache line maintenance operations by MVA, for a Harvard cache implementation:

0x0 None supported.
Configurations

Must be interpreted with ID_MMFR0_EL1, ID_MMFR2_EL1, ID_MMFR3_EL1, and ID_MMFR4_EL1. See:

Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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