|Home > Register descriptions > AArch64 system registers > MPIDR_EL1, Multiprocessor Affinity Register, EL1|
The MPIDR_EL1 provides an additional core identification mechanism for scheduling purposes in a cluster.
MPIDR_EL1 is a 64-bit register, and is part of the Other system control registers functional group.
This register is Read Only.
Affinity level 3. Highest level affinity field.
Indicates a single core system, as distinct from core 0 in a cluster. This value is:
||Core is part of a multiprocessor system. This is the value for implementations with more than one core, and for implementations with an ACE or CHI master interface.|
Indicates whether the lowest level of affinity consists of logical cores that are implemented using a multithreading type approach. This value is:
Performance of PEs at the lowest affinity level is very interdependent.
Affinity0 represents threads. Cortex®‑A76 is not multithreaded, but may be in a system with other cores that are multithreaded.
Affinity level 2. Second highest level affinity field.
Part of Affinity level 1. Third highest level affinity field.
|CPUID||Identification number for each CPU in the Cortex‑A76 cluster:|
|MP1: CPUID: 0.||to|
|MP8: CPUID: 7.|
MPIDR_EL1[31:0] is mapped to external register EDDEVAFF0.
MPIDR_EL1[63:32] is mapped to external register EDDEVAFF1.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.