B2.94 TCR_EL1, Translation Control Register, EL1

The TCR_EL1 determines which Translation Base registers define the base address register for a translation table walk required for stage 1 translation of a memory access from EL0 or EL1 and holds cacheability and shareability information.

Bit field descriptions

TCR_EL1 is a 64-bit register, and is part of the Virtual memory control registers functional group.

Figure B2-78 TCR_EL1 bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Note:

Bits[50:39], architecturally defined, are implemented in the core.

HD, [40]

Hardware management of dirty state in stage 1 translations from EL0 and EL1. The possible values are:

0 Stage 1 hardware management of dirty state disabled.
1 Stage 1 hardware management of dirty state enabled, only if the HA bit is also set to 1.
HA, [39]

Hardware Access flag update in stage 1 translations from EL0 and EL1. The possible values are:

0 Stage 1 Access flag update disabled.
1 Stage 1 Access flag update enabled.
Configurations

RW fields in this register reset to UNKNOWN values.

Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

Non-ConfidentialPDF file icon PDF version100798_0301_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.