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The VTCR_EL2 controls the translation table walks required for the stage 2 translation of memory accesses from Non-secure EL0 and EL1.
It also holds cacheability and shareability information for the accesses.
VTCR_EL2 is a 32-bit register, and is part of:
Bits[28:25] and bits[22:21], architecturally defined, are implemented in the core.
TTBR0_EL2 granule size. The possible values are:
All other values are not supported.
RW fields in this register reset to architecturally UNKNOWN values.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.