D6.10 PMPIDR3, Performance Monitors Peripheral Identification Register 3

The PMPIDR3 provides information to identify a Performance Monitor component.

Bit field descriptions

The PMPIDR3 is a 32-bit register.

Figure D6-9 PMPIDR3 bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


RES0, [31:8]
res0Reserved.
REVAND, [7:4]
0x0Part minor revision.
CMOD, [3:0]
0x0Customer modified.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

The PMPIDR3 can be accessed through the external debug interface, offset 0xFEC.

Non-ConfidentialPDF file icon PDF version100798_0301_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.