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Home > Debug registers > Memory-mapped PMU registers > PMPIDR3, Performance Monitors Peripheral Identification Register 3 |
The PMPIDR3 provides information to identify a Performance Monitor component.
The PMPIDR3 is a 32-bit register.
res0 | Reserved. |
| Part minor revision. |
| Customer modified. |
Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The PMPIDR3 can be accessed through the external debug interface, offset
.0xFEC