D6.11 PMPIDR4, Performance Monitors Peripheral Identification Register 4

The PMPIDR4 provides information to identify a Performance Monitor component.

Bit field descriptions

The PMPIDR4 is a 32-bit register.

Figure D6-10 PMPIDR4 bit assignments
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RES0, [31:8]
res0Reserved.
Size, [7:4]
0x0Size of the component. Log2 the number of 4KB pages from the start of the component to the end of the component ID registers.
DES_2, [3:0]
0x4Arm Limited. This is the least significant nibble JEP106 continuation code.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

The PMPIDR4 can be accessed through the external debug interface, offset 0xFD0.

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