D9.7 TRCCCCTLR, Cycle Count Control Register

The TRCCCCTLR sets the threshold value for cycle counting.

Bit field descriptions

The TRCCCCTLR is a 32-bit register.

Figure D9-6 TRCCCCTLR bit assignments
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RES0, [31:12]
res0Reserved.
THRESHOLD, [11:0]
Instruction trace cycle count threshold.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

The TRCCCCTLR can be accessed through the external debug interface, offset 0x038.

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