D9.32 TRCIDR3, ID Register 3

The TRCIDR3 indicates:

  • Whether TRCVICTLR is supported.
  • The number of cores available for tracing.
  • If an Exception level supports instruction tracing.
  • The minimum threshold value for instruction trace cycle counting.
  • Whether the synchronization period is fixed.
  • Whether TRCSTALLCTLR is supported and if so whether it supports trace overflow prevention and supports stall control of the core.

Bit field descriptions

The TRCIDR3 is a 32-bit register.

Figure D9-30 TRCIDR3 bit assignments
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Indicates whether TRCSTALLCTLR.NOOVERFLOW is implemented:

0TRCSTALLCTLR.NOOVERFLOW is not implemented.
NUMPROC, [30:28]

Indicates the number of cores available for tracing:

0b000The trace unit can trace one core, ETM trace unit sharing not supported.

Indicates whether stall control is implemented:

1The system supports core stall control.

Indicates whether TRCSTALLCTLR is implemented:

1TRCSTALLCTLR is implemented.

This field is used in conjunction with SYSSTALL.

SYNCPR, [25]

Indicates whether there is a fixed synchronization period:

0TRCSYNCPR is read-write so software can change the synchronization period.
TRCERR, [24]

Indicates whether TRCVICTLR.TRCERR is implemented:

1TRCVICTLR.TRCERR is implemented.
EXLEVEL_NS, [23:20]

Each bit controls whether instruction tracing in Non-secure state is implemented for the corresponding Exception level:

0b0111Instruction tracing is implemented for Non-secure EL0, EL1, and EL2 Exception levels.
EXLEVEL_S, [19:16]

Each bit controls whether instruction tracing in Secure state is implemented for the corresponding Exception level:

0b1011Instruction tracing is implemented for Secure EL0, EL1, and EL3 Exception levels.
RES0, [15:12]
CCITMIN, [11:0]

The minimum value that can be programmed in TRCCCCTLR.THRESHOLD:

0x004Instruction trace cycle counting minimum threshold is 4.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

The TRCIDR3 can be accessed through the external debug interface, offset 0x1EC.

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