D9.65 TRCSSCCR0, Single-Shot Comparator Control Register 0

The TRCSSCCR0 controls the single-shot comparator.

Bit field descriptions

The TRCSSCSR0 is a 32-bit register

Figure D9-62 TRCSSCCR0 bit assignments
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RES0, [31:25]
res0Reserved.
RST, [24]

Enables the single-shot comparator resource to be reset when it occurs, to enable another comparator match to be detected:

1Reset enabled. Multiple matches can occur.
RES0, [23:20]
res0Reserved.
ARC, [19:16]

Selects one or more address range comparators for single-shot control.

One bit is provided for each implemented address range comparator.

RES0, [15:8]
res0Reserved.
SAC, [7:0]

Selects one or more single address comparators for single-shot control.

One bit is provided for each implemented single address comparator.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

The TRCSSCCR0 can be accessed through the external debug interface, offset 0x280.

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