B2.36 DISR_EL1, Deferred Interrupt Status Register, EL1

The DISR_EL1 records the SError interrupts consumed by an ESB instruction.

Bit field descriptions

DISR_EL1 is a 64-bit register, and is part of the registers Reliability, Availability, Serviceability (RAS) functional group.

Figure B2-32 DISR_EL1 bit assignments, DISR_EL1.IDS is 0
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RES0, [63:32]
Reserved, RES0.
A, [31]

Set to 1 when ESB defers an asynchronous SError interrupt. If the implementation does not include any synchronizable sources of SError interrupt, this bit is res0.

RES0, [30:25]
Reserved, RES0.
IDS, [24]

Indicates the type of format the deferred SError interrupt uses. The value of this bit is:

0

Deferred error uses architecturally-defined format.

RES0, [23:13]
Reserved, RES0.
AET, [12:10]
Asynchronous Error Type. Describes the state of the core after taking an asynchronous Data Abort exception. The possible values are:
000Uncontainable error (UC).
001Unrecoverable error (UEU).

Note:

The recovery software must also examine any implemented fault records to determine the location and extent of the error.

EA, [9]
Reserved, RES0.
RES0, [8:6]
Reserved, RES0.
DFSC, [5:0]

Data Fault Status Code. The possible values of this field are:

010001

Asynchronous SError interrupt.

Note:

In AArch32 the 010001 code previously meant an Asynchronous External Abort on memory access. With the RAS extension, it extends to include any asynchronous SError interrupt. The Parity Error codes are not used in the RAS extension.
Configurations

There are no configuration notes.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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