|Home > Register descriptions > AArch64 system registers > TCR_EL2, Translation Control Register, EL2|
The TCR_EL2 controls translation table walks required for stage 1 translation of a memory access from EL2 and holds cacheability and shareability information.
TCR_EL2 is a 32-bit register.
TCR_EL2 is part of:
Bits[28:21], architecturally defined, are implemented in the core.
Dirty bit update. The possible values are:
|Dirty bit update is disabled.|
|Dirty bit update is enabled.|
Stage 1 Access flag update. The possible values are:
|Stage 1 Access flag update is disabled.|
|Stage 1 Access flag update is enabled.|
When the Virtualization Host Extension is activated, TCR_EL2 has the same bit assignments as TCR_EL1.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.