B2.96 TCR_EL3, Translation Control Register, EL3

The TCR_EL3 controls translation table walks required for stage 1 translation of memory accesses from EL3 and holds cacheability and shareability information for the accesses.

Bit field descriptions

TCR_EL3 is a 32-bit register and is part of the Virtual memory control registers functional group.

Figure B2-80 TCR_EL3 bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Note:

Bits[28:21], architecturally defined, are implemented in the core.

HD, [22]

Dirty bit update. The possible values are:

0Dirty bit update is disabled.
1Dirty bit update is enabled.
HA, [21]

Stage 1 Access flag update. The possible values are:

0Stage 1 Access flag update is enabled.
1Stage 1 Access flag update is disabled.
Configurations

There are no configuration notes.

Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

Non-ConfidentialPDF file icon PDF version100798_0301_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.