|Home > Functional description > Power management > Power up and down sequences|
The following approach allows taking the Cortex®‑A76 cores in the cluster in and out of coherence.
To take a core out of coherence ready for core powerdown, the following power down steps must be performed:
All L1 and L2 cache disabling, L1 and L2 cache flushing, and communication
with the L3 memory system is performed in hardware after the
executed, under the direction of the power controller.
WFIinstruction when the CPUPWRCTLR.CORE_PWRDN_EN bit is set automatically masks out all interrupts and wake-up events in the core. If executed when the CPUPWRCTLR.CORE_PWRDN_EN bit is set the WFI never wakes up and the core needs to be reset to restart.
For information about cluster powerdown, see the Arm® DynamIQ™ Shared Unit Technical Reference Manual.
To bring a core into coherence after reset, no software steps are required.