A6.6.4 Encoding for the L2 TLB

The following section describes the encoding for L2 TLB direct accesses.

The following table shows the encoding that is required to select a given TLB entry.

Table A6-30 L2 TLB encoding

Bit fields of Rd Description
[31:24] RAMID = 0x18
[23:21] Reserved
[20:18] Way
000way0
001way1
010way2
011way3
100way4
[17:8] Reserved
[7:0] Index

The following table shows the data that is returned from accessing the L2 TLB.

Table A6-31 L2 TLB format

Register Bit field Description
Instruction Register 0 [63:59]

Reserved

[58] Non-global
[57] Outer-shared
[56] Inner-shared
[55] Reserved
[54:52]

Memory attributes:

000Device nGnRnE
001Device nGnRE
010Device nGRE
011Device GRE
100Non-cacheable
101Write-Back No-Allocate
110Write-Back Transient
111Write-Back Read-Allocate and Write-Allocate
[51:48]

Reserved

[47:20] Physical address [39:12]
[19:17]

Page size:

0004KB
00116KB
01064KB
011256KB
1002MB
10132MB
110512MB
1111GB
[16:7] Reserved
[6] Indicates that the entry is coalesced and holds translations for four contiguous pages
[5:2] This bit field contains the valid bits for four contiguous pages. If the entry is non-coalesced, then 0b0001 indicates a valid entry.
[1:0] Reserved
Instruction Register 1 [63:54]

VMID [9:0]

[53:38] ASID [15:0]
[37] Walk cache entry
[36] Prefetched translation
[35:7] Virtual address [48:20]
[6] Non-secure
[5:0] Reserved
Instruction Register 2 [63:8]

Reserved

[7:6]

Translation regime:

00Secure EL1
01EL3
10Non-secure EL1
11EL2
[5:0] VMID [15:10]
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