A8.6 Error recording
The component that detects an error is called a node. The Cortex®‑A76 core is a node that interacts with the DynamIQ™ Shared Unit node. There is one record per node for the errors detected.
For more information on error recording generated by cache protection, see the Arm® Reliability, Availability, and
Serviceability (RAS) Specification, Armv8, for the Armv8-A
architecture profile. The following points apply
specifically to the Cortex‑A76
- Error recording is only available when the core cache protection is implemented.
- In the Cortex‑A76 core, any error that is detected is reported and recorded in the
error record registers:
- B2.38 ERRSELR_EL1, Error Record Select Register, EL1
- B2.39 ERXADDR_EL1, Selected Error Record Address Register, EL1
- B2.40 ERXCTLR_EL1, Selected Error Record Control Register, EL1
- B2.41 ERXFR_EL1, Selected Error Record Feature Register, EL1
- B2.42 ERXMISC0_EL1, Selected Error Record Miscellaneous Register 0, EL1
- B2.43 ERXMISC1_EL1, Selected Error Record Miscellaneous Register 1, EL1
- B2.44 ERXPFGCDNR_EL1,
Selected Error Pseudo Fault Generation Count Down Register, EL1
- B2.45 ERXPFGCTLR_EL1,
Selected Error Pseudo Fault Generation Control Register, EL1
- B2.46 ERXPFGFR_EL1,
Selected Pseudo Fault Generation Feature Register, EL1
- B2.47 ERXSTATUS_EL1, Selected Error Record Primary Status Register, EL1
- There are two error records provided, which can be selected with the ERRSELR_EL1
- Record 0 is private to the core, and is updated on any error in the core RAMs
including L1 caches, TLB, and L2 cache.
- Record 1 records any error in the L3 and snoop filter RAMs and is shared between all
cores in the cluster.
- The fault handling interrupt is generated on the nFAULTIRQ pin for L3 and snoop filter errors, or
on the nFAULTIRQ[n+1] pin
for core n L1 and L2 errors.