|Home > Debug registers > AArch64 AMU registers > AMUSERENR_EL0, Activity Monitor EL0 Enable access, EL0|
The AMUSERENR_EL0 enables or disables EL0 access to the activity monitors.
The AMUSERENR_EL0 is a 32-bit register.
Traps EL0 accesses to the activity monitor registers to EL1. The possible values are:
|0||EL0 accesses to the activity monitor registers are trapped to EL1.|
|1||EL0 accesses to the activity monitor registers are not trapped to EL1. Software can access all activity monitor registers at EL0.|
To access the AMUSERENR_EL0:
MRS <Xt>, AMUSERENR_EL0 ; Read AMUSERENR_EL0 into Xt MSR AMUSERENR_EL0, <Xt> ; Write Xt to AMUSERENR_EL0
Register access is encoded as follows:
Table D8-5 AMUSERENR_EL0 encoding
This register is accessible as follows:
If ACTLR_EL2.AMEN is 0, then Non-secure accesses to this register from EL0 and EL1 are trapped to EL2.
If ACTLR_EL3.AMEN is 0, then accesses to this register from EL0, EL1, and EL2 are trapped to EL3.