D3.14 EDRCR, External Debug Reserve Control Register

Bit field descriptions

Figure D3-12 EDRCR bit assignments
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RES0, [31:4]
res0Reserved.
CSPA, [3]

Clear Sticky Pipeline Advance. This bit is used to clear the EDSCR.PipeAdv bit to 0. The actions on writing to this bit are:

0No action.
1Clear the EDSCR.PipeAdv bit to 0.
CSE, [2]

Clear Sticky Error. Used to clear the EDSCR cumulative error bits to 0. The actions on writing to this bit are:

0No action
1Clear the EDSCR.{TXU, RXO, ERR} bits, and, if the core is in Debug state, the EDSCR.ITO bit, to 0.
RES0, [1:0]
res0Reserved.

The EDRCR can be accessed through the internal memory-mapped interface and the external debug interface, offset 0x090.

Usage constraints

This register is accessible as follows:

Off DLK OSLK SLK Default
Error Error Error WI WO
Configurations

EDRCR is in the Core power domain.

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