D9.5 TRCAUXCTLR, Auxiliary Control Register

The TRCAUXCTLR provides implementation defined configuration and control options.

Bit field descriptions

Figure D9-4 TRCAUXCTLR bit assignments
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RES0, [31:8]
res0Reserved.
CIFOVERRIDE, [7]

Override core interface register repeater clock enable. The possible values are:

0Core interface clock gate is enabled.
1Core interface clock gate is disabled.
INOVFLOWEN, [6]

Allow overflows of the core interface buffer, removing any rare impact that the trace unit might have on the core's speculation when enabled. The possible values are:

0Core interface buffer overflows are disabled.
1Core interface buffer overflows are enabled.

When this bit is set to 1, the trace start/stop logic might deviate from architecturally-specified behavior.

FLUSHOVERRIDE, [5]

Override ETM flush behavior. The possible values are:

0ETM trace unit FIFO is flushed and ETM trace unit enters idle state when DBGEN or NIDEN is LOW.
1ETM trace unit FIFO is not flushed and ETM trace unit does not enter idle state when DBGEN or NIDEN is LOW.

When this bit is set to 1, the trace unit behavior deviates from architecturally-specified behavior.

TSIOVERRIDE, [4]

Override TS packet insertion behavior. The possible values are:

0Timestamp packets are inserted into FIFO only when trace activity is LOW.
1Timestamp packets are inserted into FIFO irrespective of trace activity.
SYNCOVERRIDE, [3]

Override SYNC packet insertion behavior. The possible values are:

0SYNC packets are inserted into FIFO only when trace activity is low.
1SYNC packets are inserted into FIFO irrespective of trace activity.
FRSYNCOVFLOW, [2]

Force overflows to output synchronization packets. The possible values are:

0No FIFO overflow when SYNC packets are delayed.
1Forces FIFO overflow when SYNC packets are delayed.

When this bit is set to 1, the trace unit behavior deviates from architecturally-specified behavior.

IDLEACKOVERRIDE, [1]

Force ETM idle acknowledge. The possible values are:

0ETM trace unit idle acknowledge is asserted only when the ETM trace unit is in idle state.
1ETM trace unit idle acknowledge is asserted irrespective of the ETM trace unit idle state.

When this bit is set to 1, trace unit behavior deviates from architecturally-specified behavior.

AFREADYOVERRIDE, [0]

Force assertion of AFREADYM output. The possible values are:

0ETM trace unit AFREADYM output is asserted only when the ETM trace unit is in idle state or when all the trace bytes in FIFO before a flush request are output.
1ETM trace unit AFREADYM output is always asserted HIGH.

When this bit is set to 1, trace unit behavior deviates from architecturally-specified behavior.

The TRCAUXCTLR can be accessed through the internal memory-mapped interface and the external debug interface, offset 0x018.

Configurations
Available in all configurations.
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