B2.93 SCTLR_EL3, System Control Register, EL3

The SCTLR_EL3 provides top-level control of the system, including its memory system at EL3.

Bit field descriptions

SCTLR_EL3 is a 32-bit register, and is part of the Other system control registers functional group.

This register resets to 0x30C50838.

Figure B2-77 SCTLR_EL3 bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

RES0, [31:30]


RES1, [29:28]


RES0, [27:26]


EE, [25]

Exception endianness. This bit controls the endianness for:

  • Explicit data accesses at EL3.
  • Stage 1 translation table walks at EL3.

The possible values are:

0Little endian.
1Big endian.

The reset value is determined by the CFGEND configuration signal.

I, [12]

Global instruction cache enable. The possible values are:

0Instruction caches disabled. This is the reset value.
1Instruction caches enabled.
C, [2]

Global enable for data and unifies caches. The possible values are:

0Disables data and unified caches. This is the reset value.
1Enables data and unified caches.
M, [0]

Global enable for the EL3 MMU. The possible values are:

0Disables EL3 MMU. This is the reset value.
1Enables EL3 MMU.

There are no configuration notes.

Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

Non-ConfidentialPDF file icon PDF version100798_0301_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.