Using this book

This book is organized into the following chapters:

Part A Functional description

This part describes the main functionality of the Cortex®‑A76 core.

Chapter A1 Introduction

This chapter provides an overview of the Cortex®‑A76 core and its features.

Chapter A2 Technical overview

This chapter describes the structure of the Cortex®‑A76 core.

Chapter A3 Clocks, resets, and input synchronization

This chapter describes the clocks, resets, and input synchronization of the Cortex®‑A76 core.

Chapter A4 Power management

This chapter describes the power domains and the power modes in the Cortex®‑A76 core.

Chapter A5 Memory Management Unit

This chapter describes the Memory Management Unit (MMU) of the Cortex®‑A76 core.

Chapter A6 Level 1 memory system

This chapter describes the L1 instruction cache and data cache that make up the L1 memory system.

Chapter A7 Level 2 memory system

This chapter describes the L2 memory system.

Chapter A8 Reliability, Availability, and Serviceability (RAS)

This chapter describes the RAS features implemented in the Cortex®‑A76 core.

Chapter A9 Generic Interrupt Controller CPU interface

This chapter describes the Cortex®‑A76 core implementation of the Arm Generic Interrupt Controller (GIC) CPU interface.

Chapter A10 Advanced SIMD and floating-point support

This chapter describes the Advanced SIMD and floating-point features and registers in the Cortex®‑A76 core. The unit in charge of handling the Advanced SIMD and floating-point features is also referred to as data engine in this manual.

Part B Register descriptions

This part describes the non-debug registers of the Cortex®‑A76 core.

Chapter B1 AArch32 system registers

This chapter describes the system registers in the AArch32 state.

Chapter B2 AArch64 system registers

This chapter describes the system registers in the AArch64 state.

Chapter B3 Error system registers

This chapter describes the error registers accessed by the AArch64 error registers.

Chapter B4 GIC registers

This chapter describes the GIC registers.

Chapter B5 Advanced SIMD and floating-point registers

This chapter describes the Advanced SIMD and floating-point registers.

Part C Debug descriptions

This part describes the debug functionality of the Cortex®‑A76 core.

Chapter C1 Debug

This chapter describes the Cortex®‑A76 core debug registers and shows examples of how to use them.

Chapter C2 Performance Monitor Unit

This chapter describes the Performance Monitor Unit (PMU) and the registers that it uses.

Chapter C3 Activity Monitor Unit

This chapter describes the Activity Monitor Unit (AMU).

Chapter C4 Embedded Trace Macrocell

This chapter describes the ETM for the Cortex®‑A76 core.

Part D Debug registers

This part describes the debug registers of the Cortex®‑A76 core.

Chapter D1 AArch32 debug registers

This chapter describes the debug registers in the AArch32 Execution state and shows examples of how to use them.

Chapter D2 AArch64 debug registers

This chapter describes the debug registers in the AArch64 Execution state and shows examples of how to use them.

Chapter D3 Memory-mapped debug registers

This chapter describes the memory-mapped debug registers and shows examples of how to use them.

Chapter D4 AArch32 PMU registers

This chapter describes the AArch32 PMU registers and shows examples of how to use them.

Chapter D5 AArch64 PMU registers

This chapter describes the AArch64 PMU registers and shows examples of how to use them.

Chapter D6 Memory-mapped PMU registers

This chapter describes the memory-mapped PMU registers and shows examples of how to use them.

Chapter D7 PMU snapshot registers

PMU snapshot registers are an IMPLEMENTATION DEFINED extension to an Arm®v8‑A compliant PMU to support an external core monitor that connects to a system profiler.

Chapter D8 AArch64 AMU registers

This chapter describes the AArch64 AMU registers and shows examples of how to use them.

Chapter D9 ETM registers

This chapter describes the ETM registers.

E Appendices

This part describes the appendices of the Cortex®‑A76 core.

Appendix A Cortex®‑A76 Core AArch32 UNPREDICTABLE behaviors

This appendix describes the cases in which the Cortex®‑A76 core implementation diverges from the preferred behavior described in Armv8 AArch32 UNPREDICTABLE behaviors.

Appendix B Revisions

This appendix describes the technical changes between released issues of this book.

Glossary

The Arm® Glossary is a list of terms used in Arm documentation, together with definitions for those terms. The Arm Glossary does not contain terms that are industry standard unless the Arm meaning differs from the generally accepted meaning.

See the Arm® Glossary for more information.

Typographic conventions

italic
Introduces special terminology, denotes cross-references, and citations.
bold
Highlights interface elements, such as menu names. Denotes signal names. Also used for terms in descriptive lists, where appropriate.
monospace
Denotes text that you can enter at the keyboard, such as commands, file and program names, and source code.
monospace
Denotes a permitted abbreviation for a command or option. You can enter the underlined text instead of the full command or option name.
monospace italic
Denotes arguments to monospace text where the argument is to be replaced by a specific value.
monospace bold
Denotes language keywords when used outside example code.
<and>
Encloses replaceable terms for assembler syntax where they appear in code or code fragments. For example:
MRC p15, 0, <Rd>, <CRn>, <CRm>, <Opcode_2>
SMALL CAPITALS
Used in body text for a few terms that have specific technical meanings, that are defined in the Arm® Glossary. For example, IMPLEMENTATION DEFINED, IMPLEMENTATION SPECIFIC, UNKNOWN, and UNPREDICTABLE.

Timing diagrams

The following figure explains the components used in timing diagrams. Variations, when they occur, have clear labels. You must not assume any timing information that is not explicit in the diagrams.

Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the shaded area at that time. The actual level is unimportant and does not affect normal operation.

Figure 1 Key to timing diagram conventions
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Signals

The signal conventions are:

Signal level

The level of an asserted signal depends on whether the signal is active-HIGH or active-LOW. Asserted means:

  • HIGH for active-HIGH signals.

  • LOW for active-LOW signals.

Lowercase n

At the start or end of a signal name denotes an active-LOW signal.

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