|Home > Functional description > Memory Management Unit > TLB match process|
The Armv8-A architecture provides support for multiple maps from the VA space that are translated differently.
TLB entries store the context information required to facilitate a match and avoid the need for a TLB flush on a context or virtual machine switch.
Each TLB entry contains a:
Each entry is either associated with a particular ASID or global. In addition, each TLB entry contains a field to store the VMID in the entry applicable to accesses from Non-secure EL0 and EL1 Exception levels.
Each entry is associated with a particular translation regime.
A TLB match entry occurs when the following conditions are met:
ASID is relevant when the translation regime is:
VMID is relevant for EL1 or EL0 in Non-secure state.