A6.2 Cache behavior
The implementation specific features of the instruction and data caches include:
- At reset the instruction and data caches are disabled and both caches are
Note: The L1 instruction and data caches are invalidated automatically at
reset unless the DISCACHEINVLD signal is set HIGH when the Cortex®‑A76 core is reset. This
signal must only be used in diagnostic mode. If caches are not invalidated on reset, their
functionality cannot be guaranteed. See the
Shared Unit Technical Reference Manual for more information on
- You can enable or disable each cache independently.
- Cache lockdown is not supported.
- On a cache miss, data for the cache linefill is requested in critical