A6.2 Cache behavior

The implementation specific features of the instruction and data caches include:

  • At reset the instruction and data caches are disabled and both caches are automatically invalidated.

Note:

The L1 instruction and data caches are invalidated automatically at reset unless the DISCACHEINVLD signal is set HIGH when the Cortex®‑A76 core is reset. This signal must only be used in diagnostic mode. If caches are not invalidated on reset, their functionality cannot be guaranteed. See the Arm® DynamIQ™ Shared Unit Technical Reference Manual for more information on DISCACHEINVLD.
  • You can enable or disable each cache independently.
  • Cache lockdown is not supported.
  • On a cache miss, data for the cache linefill is requested in critical word-first order.
Non-ConfidentialPDF file icon PDF version100798_0301_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.