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The integrated L2 cache is the Point of Unification for the Cortex®‑A76 core. It handles both instruction and data requests from the instruction side and data side of each core respectively.
When fetched from the system, instructions are allocated to the L2 cache and can be invalidated during maintenance operations.
The L2 cache is invalidated automatically at reset unless the DISCACHEINVLD signal is set HIGH when the Cortex‑A76 core is reset. This signal must be used only in diagnostic mode. If caches are not invalidated on reset, their functionality cannot be guaranteed. See the Arm® DynamIQ™ Shared Unit Technical Reference Manual for more information on the DISCACHEINVLD signal.