B2.18 CCSIDR_EL1, Cache Size ID Register, EL1

The CCSIDR_EL1 provides information about the architecture of the currently selected cache.

Bit field descriptions

CCSIDR_EL1 is a 32-bit register, and is part of the Identification registers functional group.

This register is Read Only.

Figure B2-14 CCSIDR_EL1 bit assignments
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WT, [31]

Indicates whether the selected cache level supports Write-Through:

0

Cache Write-Through is not supported at any level.

For more information about encoding, see CCSIDR_EL1 encodings.

WB, [30]

Indicates whether the selected cache level supports Write-Back. Permitted values are:

0

Write-Back is not supported.

1

Write-Back is supported.

For more information about encoding, see CCSIDR_EL1 encodings.

RA, [29]

Indicates whether the selected cache level supports read-allocation. Permitted values are:

0

Read-allocation is not supported.

1

Read-allocation is supported.

For more information about encoding, see CCSIDR_EL1 encodings.

WA, [28]

Indicates whether the selected cache level supports write-allocation. Permitted values are:

0

Write-allocation is not supported.

1

Write-allocation is supported.

For more information about encoding, see CCSIDR_EL1 encodings.

NumSets, [27:13]

(Number of sets in cache) - 1. Therefore, a value of 0 indicates one set in the cache. The number of sets does not have to be a power of 2.

For more information about encoding, see CCSIDR_EL1 encodings.

Associativity, [12:3]

(Associativity of cache) - 1. Therefore, a value of 0 indicates an associativity of 1. The associativity does not have to be a power of 2.

For more information about encoding, see CCSIDR_EL1 encodings.

LineSize, [2:0]

(Log2(Number of bytes in cache line)) - 4. For example:

Indicates the (log2 (number of words in cache line)) - 2:

For a line length of 16 bytes: Log2(16) = 4, LineSize entry = 0. This is the minimum line length.

For a line length of 32 bytes: Log2(32) = 5, LineSize entry = 1.

For more information about encoding, see CCSIDR_EL1 encodings.

Configurations
There are no configuration notes.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

CCSIDR_EL1 encodings

The following table shows the individual bit field and complete register encodings for the CCSIDR_EL1.

Table B2-6 CCSIDR encodings

CSSELR Cache Size Complete register encoding Register bit field encoding
Level InD WT WB RA WA NumSets Associativity LineSize
0b000 0b0 L1 Data cache 64KB 701FE01A 0 1 1 1 0x00FF 0x003 2
0b000 0b1 L1 Instruction cache 64KB 201FE01A 0 0 1 0 0x00FF 0x003 2
0b001 0b0 L2 cache 128KB 701FE03A 0 1 1 1 0x00FF 0x007 2
256KB 703FE03A 0 1 1 1 0x01FF 0x007 2
512KB 707FE03A 0 1 1 1 0x03FF 0x007 2
0b001 0b1 Reserved - - - - - - - - -
0b010 0b0 Reserved - - - - - - - - -
0b010 0b1 Reserved - - - - - - - - -
0b0101 - 0b1111 Reserved - - - - - - - - -
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