D5.3 PMCEID1_EL0, Performance Monitors Common Event Identification Register 1, EL0

The PMCEID1_EL0 defines which common architectural and common microarchitectural feature events are implemented.

Bit field descriptions

Figure D5-2 PMCEID1_EL0 bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


RES0, [31:16]
res0Reserved.
ID[47:32], [15:0]

Common architectural and microarchitectural feature events that can be counted by the PMU event counters.

For each bit described in the following table, the event is implemented if the bit is set to 1, or not implemented if the bit is set to 0.

Table D5-3 PMU common events

Bit Event mnemonic Description
[15] L2D_TLB Attributable Level 2 data or unified TLB access.
1This event is implemented.
[13] L2D_TLB_REFILL Attributable Level 2 data or unified TLB refill.
1This event is implemented.
[6] L1I_TLB Level 1 instruction TLB access.
1This event is implemented.
[5] L1D_TLB Level 1 data TLB access.
1This event is implemented.
[4] STALL_BACKEND No operation issued due to backend.
1This event is implemented.
[3] STALL_FRONTEND No operation issued due to frontend.
1This event is implemented.
[2] BR_MIS_PRED_RETIRED Instruction architecturally executed, mispredicted branch.
1This event is not implemented.
[1] BR_RETIRED Instruction architecturally executed, branch.
1This event is implemented.
[0] L2D_CACHE_ALLOCATE Level 2 data cache allocation without refill.
1This event is implemented.

Note:

The PMU events implemented in the above table can be found in Table   C2-1 .
Non-ConfidentialPDF file icon PDF version100798_0301_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.