B3.9 ERR0PFGFR, Error Pseudo Fault Generation Feature Register

The ERR0PFGFR is the Cortex®‑A76 node register that defines which fault generation features are implemented.

Bit field descriptions

ERR0PFGFR is a 32-bit register and is RO.

Figure B3-7 ERR0PFGFR bit assignments
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PFG, [31]

Pseudo Fault Generation. The value is:

1The node implements a fault injection mechanism.
R, [30]

Restartable bit. When it reaches zero, the Error Generation Counter restarts from the ERR0PFGCDN value or stops. The value is:

1This feature is controllable.
[29:7]
RES0Reserved.
CE, [6]
Corrected Error generation. The value is:
1This feature is controllable.
DE, [5]
Deferred Error generation. The value is:
1This feature is controllable.
UEO, [4]
Latent or Restartable Error generation. The value is:
0The node does not support this feature.
UER, [3]
Signaled or Recoverable Error generation. The value is:
0The node does not support this feature.
UEU, [2]
Unrecoverable Error generation. The value is:
0The node does not support this feature.
UC, [1]
Uncontainable Error generation. The value is:
1This feature is controllable.
[0]
RES0Reserved.
Configurations

There are no configuration notes.

ERR0PFGFR resets to 0xC0000062.

When ERRSELR.SEL==0, ERR0PFGFR is accessible from B2.46 ERXPFGFR_EL1, Selected Pseudo Fault Generation Feature Register, EL1.

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