|Home > Debug registers > AArch64 AMU registers > AMCNTENCLR0_EL0, Activity Monitors Count Enable Clear Register, EL0|
The AMCNTENCLR0_EL0 disables the activity monitor counters implemented, AMEVCNTR0-4.
The AMCNTENCLR_EL0 is a 32-bit register.
AMEVCNTRn disable bit. The possible values are:
|0||When this bit is read, the activity counter n is disabled. When it is written, it has no effect.|
|1||When this bit is read, the activity counter n is enabled. When it is written, it disables the activity counter n.|
To access the AMCNTENCLR_EL0:
MRS <Xt>, AMCNTENCLR_EL0 ; Read AMCNTENCLR_EL0 into Xt MSR AMCNTENCLR_EL0, <Xt> ; Write <Xt> to AMCNTENCLR_EL0
Register access is encoded as follows:
Table D8-2 AMCNTENCLR_EL0 encoding
The AMCNTENCLR_EL0 can be accessed through the external debug interface,
0xC20. In this
case, it is read-only.
This register is accessible as follows:
If ACTLR_EL2.AMEN is 0, then Non-secure accesses to this register from EL0 and EL1 are trapped to EL2.
If ACTLR_EL3.AMEN is 0, then accesses to this register from EL0, EL1, and EL2 are trapped to EL3.
If AMUSERENR_EL0.EN is 0, then accesses to this register from EL0 are trapped to EL1.