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This section describes the AArch64 architectural system registers implemented in the Cortex®‑A76 core.
The section contains two tables:
This table identifies the architecturally defined registers in Cortex‑A76 that have implementation defined bit fields. The register descriptions for these registers only contain information about the implementation defined bits.
See Table B2-1 Registers with implementation defined bit fields.
This table identifies the other architecturally defined registers that are implemented in the Cortex‑A76 core. These registers are described in the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
Table B2-1 Registers with implementation defined bit fields
Table B2-2 Other architecturally defined registers
| Name | Op0 | CRn | Op1 | CRm | Op2 | Width | Description |
|---|---|---|---|---|---|---|---|
| AFSR0_EL12 | 3 | c5 | 5 | 1 | 0 | 32 | Auxiliary Fault Status Register 0 |
| AFSR1_EL12 | 3 | c5 | 5 | 1 | 1 | 32 | Auxiliary Fault Status Register 1 |
| AMAIR_EL12 | 3 | c10 | 5 | c3 | 0 | 64 | Auxiliary Memory Attribute Indirection Register |
| CNTFRQ_EL0 | 3 | c14 | 3 | 0 | 0 | 32 | Counter-timer Frequency register |
| CNTHCTL_EL2 | 3 | c14 | 4 | c1 | 0 | 32 | Counter-timer Hypervisor Control register |
| CNTHP_CTL_EL2 | 3 | c14 | 4 | c2 | 1 | 32 | Counter-timer Hypervisor Physical Timer Control register |
| CNTHP_CVAL_EL2 | 3 | c14 | 4 | c2 | 2 | 64 | Counter-timer Hyp Physical CompareValue register |
| CNTHP_TVAL_EL2 | 3 | c14 | 4 | c2 | 0 | 32 | Counter-timer Hyp Physical Timer TimerValue register |
| CNTHV_CTL_EL2 | 3 | c14 | 4 | c3 | 1 | 32 | Counter-timer Virtual Timer Control register |
| CNTHV_CVAL_EL2 | 3 | c14 | 4 | c3 | 2 | 64 | Counter-timer Virtual Timer CompareValue register |
| CNTHV_TVAL_EL2 | 3 | c14 | 4 | c3 | 0 | 32 | Counter-timer Virtual Timer TimerValue register |
| CNTKCTL_EL1 | 3 | c14 | 0 | c1 | 0 | 32 | Counter-timer Kernel Control register |
| CNTKCTL_EL12 | 3 | c14 | 5 | c1 | 0 | 32 | Counter-timer Kernel Control register |
| CNTP_CTL_EL0 | 3 | c14 | 3 | c2 | 1 | 32 | Counter-timer Physical Timer Control register |
| CNTP_CTL_EL02 | 3 | c14 | 5 | c2 | 1 | 32 | Counter-timer Physical Timer Control register |
| CNTP_CVAL_EL0 | 3 | c14 | 3 | c2 | 2 | 64 | Counter-timer Physical Timer CompareValue register |
| CNTP_CVAL_EL02 | 3 | c14 | 5 | c2 | 2 | 64 | Counter-timer Physical Timer CompareValue register |
| CNTP_TVAL_EL0 | 3 | c14 | 3 | c2 | 0 | 32 | Counter-timer Physical Timer TimerValue register |
| CNTP_TVAL_EL02 | 3 | c14 | 5 | c2 | 0 | 32 | Counter-timer Physical Timer TimerValue register |
| CNTPCT_EL0 | 3 | c14 | 3 | c0 | 1 | 64 | Counter-timer Physical Count register |
| CNTPS_CTL_EL1 | 3 | c14 | 7 | c2 | 1 | 32 | Counter-timer Physical Secure Timer Control register |
| CNTPS_CVAL_EL1 | 3 | c14 | 7 | c2 | 2 | 64 | Counter-timer Physical Secure Timer CompareValue register |
| CNTPS_TVAL_EL1 | 3 | c14 | 7 | c2 | 0 | 32 | Counter-timer Physical Secure Timer TimerValue register |
| CNTV_CTL_EL0 | 3 | c14 | 3 | c3 | 1 | 32 | Counter-timer Virtual Timer Control register |
| CNTV_CTL_EL02 | 3 | c14 | 5 | c3 | 1 | 32 | Counter-timer Virtual Timer Control register |
| CNTV_CVAL_EL0 | 3 | c14 | 3 | c3 | 2 | 64 | Counter-timer Virtual Timer CompareValue register |
| CNTV_CVAL_EL02 | 3 | c14 | 5 | c3 | 2 | 64 | Counter-timer Virtual Timer CompareValue register |
| CNTV_TVAL_EL0 | 3 | c14 | 3 | c3 | 0 | 32 | Counter-timer Virtual Timer TimerValue register |
| CNTV_TVAL_EL02 | 3 | c14 | 5 | c3 | 0 | 32 | Counter-timer Virtual Timer TimerValue register |
| CNTVCT_EL0 | 3 | c14 | 3 | c0 | 2 | 64 | Counter-timer Virtual Count register |
| CNTVOFF_EL2 | 3 | c14 | 4 | c0 | 3 | 64 | Counter-timer Virtual Offset register |
| CONTEXTIDR_EL1 | 3 | c13 | 0 | c0 | 1 | 32 | Context ID Register (EL1) |
| CONTEXTIDR_EL12 | 3 | c13 | 5 | c0 | 1 | 32 | Context ID Register (EL12) |
| CONTEXTIDR_EL2 | 3 | c13 | 4 | c0 | 1 | 32 | Context ID Register (EL2) |
| CPACR_EL12 | 3 | c1 | 5 | c0 | 2 | 32 | Architectural Feature Access Control Register |
| CPTR_EL3 | 3 | c1 | 6 | c1 | 2 | 32 | Architectural Feature Trap Register (EL3) |
| DACR32_EL2 | 3 | c3 | 4 | c0 | 0 | 32 | Domain Access Control Register |
| ESR_EL12 | 3 | c5 | 5 | c2 | 0 | 32 | Exception Syndrome Register (EL12) |
| FAR_EL1 | 3 | c6 | 0 | c0 | 0 | 64 | Fault Address Register (EL1) |
| FAR_EL12 | 3 | c6 | 5 | c0 | 0 | 64 | Fault Address Register (EL12) |
| FAR_EL2 | 3 | c6 | 4 | c0 | 0 | 64 | Fault Address Register (EL2) |
| FAR_EL3 | 3 | c6 | 6 | c0 | 0 | 64 | Fault Address Register (EL3) |
| FPEXC32_EL2 | 3 | c5 | 4 | c3 | 0 | 32 | Floating-point Exception Control register |
| HPFAR_EL2 | 3 | c6 | 4 | c0 | 4 | 64 | Hypervisor IPA Fault Address Register |
| HSTR_EL2 | 3 | c1 | 4 | c1 | 3 | 32 | Hypervisor System Trap Register |
| ID_AA64AFR0_EL1 | 3 | c0 | 0 | c5 | 4 | 64 | AArch64 Auxiliary Feature Register 0 |
| ID_AA64AFR1_EL1 | 3 | c0 | 0 | c5 | 5 | 64 | AArch64 Auxiliary Feature Register 1 |
| ID_AA64DFR1_EL1 | 3 | c0 | 0 | c5 | 1 | 64 | AArch64 Debug Feature Register 1 |
| ID_AA64PFR1_EL1 | 3 | c0 | 0 | c4 | 1 | 64 | AArch64 Core Feature Register 1 |
| ISR_EL1 | 3 | c12 | 0 | c1 | 0 | 32 | Interrupt Status Register |
| LOREA_EL1 | 3 | c10 | 0 | c4 | 1 | 64 | LORegion End Address Register |
| LORSA_EL1 | 3 | c10 | 0 | c4 | 0 | 64 | LORegion Start Address Register |
| MAIR_EL1 | 3 | c10 | 0 | c2 | 0 | 64 | Memory Attribute Indirection Register (EL1) |
| MAIR_EL12 | 3 | c10 | 5 | c2 | 0 | 64 | Memory Attribute Indirection Register (EL12) |
| MAIR_EL2 | 3 | c10 | 4 | c2 | 0 | 64 | Memory Attribute Indirection Register (EL2) |
| MAIR_EL3 | 3 | c10 | 6 | c2 | 0 | 64 | Memory Attribute Indirection Register (EL3) |
| MDCR_EL2 | 3 | c1 | 4 | c1 | 1 | 32 | Monitor Debug Configuration Register |
| MVFR0_EL1 | 3 | c0 | 0 | c3 | 0 | 32 | AArch32 Media and VFP Feature Register 0 |
| MVFR1_EL1 | 3 | c0 | 0 | c3 | 1 | 32 | AArch32 Media and VFP Feature Register 1 |
| MVFR2_EL1 | 3 | c0 | 0 | c3 | 2 | 32 | AArch32 Media and VFP Feature Register 2 |
| RMR_EL3 | 3 | c12 | 6 | c0 | 2 | 32 | Reset Management Register |
| SCR_EL3 | 3 | c1 | 6 | c1 | 0 | 32 | Secure Configuration Register |
| SDER32_EL3 | 3 | c1 | 6 | c1 | 1 | 32 | AArch32 Secure Debug Enable Register |
| TCR_EL12 | 3 | c2 | 5 | c0 | 2 | 64 | Translation Control Register (EL12) |
| TPIDR_EL0 | 3 | c13 | 3 | c0 | 2 | 64 | EL0 Read/Write Software Thread ID Register |
| TPIDR_EL1 | 3 | c13 | 0 | c0 | 4 | 64 | EL1 Software Thread ID Register |
| TPIDR_EL2 | 3 | c13 | 4 | c0 | 2 | 64 | EL2 Software Thread ID Register |
| TPIDR_EL3 | 3 | c13 | 6 | c0 | 2 | 64 | EL3 Software Thread ID Register |
| TPIDRRO_EL0 | 3 | c13 | 3 | c0 | 3 | 64 | EL0 Read-Only Software Thread ID Register |
| TTBR0_EL12 | 3 | c2 | 5 | c0 | 0 | 64 | Translation Table Base Register 0 (EL12) |
| TTBR1_EL12 | 3 | c2 | 5 | c0 | 1 | 64 | Translation Table Base Register 1 (EL12) |
| VBAR_EL1 | 3 | c12 | 0 | c0 | 0 | 64 | Vector Base Address Register (EL1) |
| VBAR_EL12 | 3 | c12 | 5 | c0 | 0 | 64 | Vector Base Address Register (EL12) |
| VBAR_EL2 | 3 | c12 | 4 | c0 | 0 | 64 | Vector Base Address Register (EL2) |
| VBAR_EL3 | 3 | c12 | 6 | c0 | 0 | 64 | Vector Base Address Register (EL3) |
| VMPIDR_EL2 | 3 | c0 | 4 | c0 | 5 | 64 | Virtualization Multiprocessor ID Register |
| VPIDR_EL2 | 3 | c0 | 4 | c0 | 0 | 32 | Virtualization Core ID Register |
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