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To support testing of error handling software, the Cortex®‑A76 core can inject errors in the error detection logic.
The following table describes all the possible types of error that the core can encounter and therefore inject.
Table A8-3 Errors injected in the Cortex‑A76 core
|Corrected errors||A CE is generated for a single-bit ECC error on L1 data caches and L2 caches, both on data and tag RAMs.|
|Deferred errors||A DE is generated for a double-bit ECC error on L1 data caches and L2 caches, but only on data RAM.|
|Uncorrected errors||A UE is generated for a double-bit ECC error on L1 data caches and L2 caches, but only on tag RAM.|
The following table describes the registers that handle error injection in the Cortex‑A76 core.
Table A8-4 Error injection registers
|ERR0PFGFR_EL1||The ERR Pseudo Fault Generation Feature register defines which errors can be injected.|
|ERR0PFGCTLR_EL1||The ERR Pseudo Fault Generation Control register controls the errors that are injected.|
|ERR0PFGCDNR_EL1||The ERR Pseudo Fault Generation Count Down register controls the fault injection timing.|