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Home > Register descriptions > GIC registers > ICC_AP1R0_EL1, Interrupt Controller Active Priorities Group 1 Register 0 EL1 |
The ICC_AP1R0_EL1 provides information about Group 1 active priorities.
This register is a 32-bit register and is part of:
The core implements 5 bits of priority with 32 priority levels, corresponding to the 32 bits [31:0] of the register. The possible values for each bit are:
0x00000000 | No interrupt active. This is the reset value. |
0x00000001 | Interrupt active for priority 0x0 . |
0x00000002 | Interrupt active for priority 0x8 . |
... | |
0x80000000 | Interrupt active for priority 0xF8 . |
Details not provided in this description are architecturally defined. See the Arm® Generic Interrupt Controller Architecture Specification.