|Home > Appendices > Cortex‑A76 Core AArch32 UNPREDICTABLE behaviors > Use of R15 by Instruction|
If the use of R15 as a base register for a load or store is unpredictable, the value used by the load or store using R15 as a base register is the Program Counter (PC) with its usual offset and, in the case of T32 instructions, with the forced word alignment. In this case, if the instruction specifies Writeback, then the load or store is performed without Writeback.
The Cortex®‑A76 core does not implement a Read 0 or Ignore Write policy on unpredictable use of R15 by instruction. Instead, the Cortex‑A76 core takes an undefined exception trap.