B3.6 ERR0MISC1, Error Record Miscellaneous Register 1

This register is unused in the Cortex®‑A76 core and marked as RES0.

Configurations

When ERRSELR.SEL==0, ERR0MISC1 is accessible from B2.48 ERXMISC1_EL1, Selected Error Record Miscellaneous Register 1, EL1.

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