B3.5 ERR0MISC0, Error Record Miscellaneous Register 0

Bit field descriptions

ERR0MISC0 is a 64-bit register, and is part of the Reliability, Availability, Serviceability (RAS) registers functional group.

Figure B3-4 ERR0MISC0 bit assignments
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[63:48]
Reserved, RES0.
OFO, [47]

Sticky overflow bit, other. The possible values of this bit are:

0Other counter has not overflowed.
1 Other counter has overflowed.

The fault handling interrupt is generated when the corrected fault handling interrupt is enabled and either overflow bit is set to 1.

CECO, [46:40]

Corrected error count, other. Incremented for each Corrected error that does not match the recorded syndrome.

This field resets to an IMPLEMENTATION DEFINED which might be UNKNOWN on a Cold reset. If the reset value is UNKNOWN, then the value of this field remains UNKNOWN until software initializes it.

OFR, [39]

Sticky overflow bit, repeat. The possible values of this bit are:

0Repeat counter has not overflowed.
1 Repeat counter has overflowed.

The fault handling interrupt is generated when the corrected fault handling interrupt is enabled and either overflow bit is set to 1.

CECR, [38:32]

Corrected error count, repeat. Incremented for the first recorded error, which also records other syndromes, and then again for each Corrected error that matches the recorded syndrome.

This field resets to an IMPLEMENTATION DEFINED which might be UNKNOWN on a Cold reset. If the reset value is UNKNOWN, then the value of this field remains UNKNOWN until software initializes it.

WAY, [31:28]

The encoding is dependent on the unit from which the error being recorded was detected. The possible values are:

L1 Data CacheIndicates which Tag RAM way or data RAM way detected the error. Upper 2 bits are unused.
L2 TLBIndicates which RAM has an error. The possible values are 0 (RAM 1) to 9 (RAM 10).
L1 Instruction CacheIndicates which way has the error. Upper 2 bits are unused.
[27:26]
Reserved, RES0.
SUBBANK, [25]

The encoding is dependent on the unit from which the error being recorded was detected. The possible values are:

L1 Instruction CacheIndicates which subbank has the error, valid for Instruction Data Cache. For Tag errors this field is zero.
BANK, [24:23]

The encoding is dependent on the unit from which the error being recorded was detected. The possible values are:

L2 CacheIndicates which L2 bank detected the error. Upper 1 bit is unused.
L1 Instruction CacheIndicates which bank has the error, valid for Instruction Data Cache. For Tag errors this field is zero.
SUBARRAY, [22:19]

The encoding is dependent on the unit from which the error being recorded was detected. The possible values are:

L2 CacheIndicates which L2 Tag way or data doubleword detected the error. Upper 1 bit is unused.
L1 Data CacheIndicates for L1 Data RAM which word had the error detected. For L1 Tag RAMs which bank had the error (0b0000: bank0 , 0b0001: bank1)
INDEX, [18:6]

The encoding is dependent on the unit from which the error being recorded was detected. The possible values are:

L2 CacheIndicates which index detected the error. Upper bits of the index are unused depending on the cache size.
L1 Data CacheIndicates which index detected the error. Upper bits of the index are unused depending on the cache size.
L2 TLBIndex of TLB RAM. Upper 4 bits are unused.
L1 Instruction CacheIndicates which index has the error. Upper bits of the index are unused depending on the cache size.
ARRAY, [5:4]

The encoding is dependent on the unit from which the error being recorded was detected. The possible values are:

L2 Cache

Indicates which array has the error. The possible values are:

0b00L2 Tag RAM.
0b01L2 Data RAM.
0b10TQ Data RAM.
0b11CHI Slave Error.
L1 Data Cache

Indicates which array detected the error. The possible values are:

0b00LS0 copy of Tag RAM.
0b01LS1 copy of Tag RAM.
0b10LS Data RAM.
L1 Instruction Cache

Indicates which array that detected the error, Data Array has higher priority. The possible values are:

0b0Tag.
0b1Data.
UNIT, [3:0]
Indicates the unit which detected the error. The possible values are:
0b1000L2 Cache.
0b0100L1 Data Cache.
0b0010L2 TLB.
0b0001L1 Instruction Cache.
Configurations
ERR0MISC0 resets to [63:32] is 0x00000000, [31:0] is UNKNOWN.
This register is accessible from the following registers when ERRSELR.SEL==0:
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